Method for generating wander or wander sequences

ABSTRACT

According to the invention, a frequency demultiplication circuit serves to generate wander or wander sequences having frequencies of less than 10 Hz and, in particular, less than 1 Hz. Said frequency demultiplication circuit receives, on the input side, pulse signals of a relatively high frequency and has two counter arrays (C 11 , C 12 ; C 21 , C 22 ) and a phase comparator circuit (COMg) that is connected to the outputs of said counter arrays. The counting cycle of one counter array (C 22 ) is modified with regard to the counting cycle of the other counter array (C 12 ) within a period of the respective wander to be generated or of the respective wander sequence to be generated according to a desired progression of the wander or of the wander sequence.

This application claims priority to International Application No.PCT/DE01/01621, which was published in the German language on Nov. 1,2001.

TECHNICAL FIELD OF THE INVENTION

This invention relates to a circuit arrangement to produce wander orwander sequences.

BACKGROUND OF THE INVENTION

Wander and wander sequences with a frequency below 10 Hz are used in thetesting and measurement technologies to investigate the behavior ofsignal transmission circuits toward signals with very long periods.Thus, the use of wander or wander sequences in connection withsynchronous digital signal transmission is required, as for example isindicated in the ITU-T Recommendation G.823 (03/93).

Up to this point, wander or wander sequences of the type cited abovecould only be produced through relatively high degrees of deviceengineering. In the process, function-modulating andfrequency-modulating signal generators were used, which, however, led tothe required wander amplitudes being issued at low clock frequencies andin all cases with a very high degree of circuitry.

SUMMARY OF THE INVENTION

This invention relates to a circuit arrangement to produce wander orwander sequences that have frequencies below 10 Hz, in particular below1 Hz, with a frequency divider circuit that receives impulse signals ofrelatively high frequency as incoming inputs and that issues impulsesignals of divided frequency at its output side from which therespective wander or the respective wander sequence is built.

The invention discloses a circuit arrangement of the type cited abovewith relatively little circuitry to produce wander or wander sequenceswhose frequencies lie below 10 Hz and preferably below 1 Hz.

According to one embodiment of the invention, there is a circuitarrangement where the frequency division circuit has two individualdividers, each of which encompasses a counting arrangement that receivesas incoming inputs the impulse signals mentioned having the relativelyhigh frequency, the count cycle of one counting arrangement is changedwith respect to the count cycle of the other counting arrangement withinthe period of the respective wander or wander sequence to be producedaccording to a desired shape of this wander or wander sequence, and aphase comparator circuit is connected at the outputs of the two countingarrangements, from the output of which the respective wander or therespective wander sequence can be taken.

One advantage of the invention is an especially low amount of circuitryin producing wander or wander sequences below 10 Hz and preferably below1 Hz. Using two counting arrangements, and by changing the count cycleof one counting arrangement with respect to the count cycle of the othercounting arrangement in the manner described, the prerequisites are metfor obtaining the respective desired wander or wander sequence by meansof a phase comparator circuit connected after the outputs of the twocounting arrangements.

To this end, a low pass filter is connected after the phase comparatorcircuit mentioned. This provides the advantage in that the respectivewander or respective wander sequence obtains a desired smooth shape.

It is preferable for each counting arrangement to be connected at theoutput of its own oscillator circuit. In this way, other changes can bemade in the respective wander or wander sequence if necessary bycorrespondingly controlling at least one of the two oscillator circuits.

A particular advantage is if each oscillator circuit belongs to aseparate PLL circuit. In this way, the respective wander or wandersequence can be produced with very good stability, i.e., with very lowjitter. Due to the resultant influence on the counting arrangement inthe output circuit of one of the PLL circuits, the required outputamplitude of the respective wander or wander sequence to be produced canbe produced with a high degree of stability by changing the countervalue of the affected counting arrangement within a defined count cycle.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained in more detail below with the help of thedrawings as an example.

FIG. 1 shows a block diagram of a first exemplary embodiment of thecircuit arrangement according to the invention.

FIG. 2 shows a block diagram of a second exemplary embodiment of thecircuit arrangement according to the invention.

FIG. 3 shows a diagram of the temporal shape of impulses or signals thatoccur at various points in the circuit for the circuit arrangementillustrated in FIGS. 1 and 2.

FIG. 4 shows a diagram of the temporal shape of the wander or of awander sequence that occurs at other points in the circuit for thecircuit arrangement illustrated in FIGS. 1 and 2.

DETAILED DESCRIPTION OF THE INVENTION

The circuit arrangement shown in FIG. 1 illustrates a first exemplaryembodiment, according to the invention, and encompasses a frequencydivision circuit that has two individual dividers CNTa, CNTb, each ofwhich encompasses a counting arrangement, and to which input impulses ofrelatively high frequency, for example impulses with a frequency of 8kHz, are fed at a common input connection IN that can be derived fromimpulses with a frequency of, for example, 16,384 MHz. The generatorcircuit that produces these impulses operate at very high precision(10⁻¹²) so as to be able to make available the desired wander or wandersequences. Each of the two individual dividers mentioned, CNTa, CNTb—which basically both have the same division ratio, i.e., are built inthe same way —includes a counting arrangement that is made up of twopartial, or individual counters C11, C12 and C21, C22 connected inseries, of which the partial counters C11, C21 perform a first coarsedivision of the input impulses and of which the partial counters C12,C22 execute the final conversion. In principle, each countingarrangement can also be made up of only one counter.

Control outputs of a control circuit CTR1 are connected to adjustmentinputs of the partial counter C22 belonging to the individual dividerCNTb and, if necessary, also to adjustment inputs of the partial counterconnected to it, C21. The affected control circuit CTR1 is connected toa control input at an input connection Cin and to a signal input at theoutput of the partial counter C22. By means of this control circuitCTR1, the count cycle of at least partial counter C22 can be changedwith respect to the count cycle of its corresponding partial counter C12belonging to the other individual divider CNTa within the determinedperiod of the respective wander or wander sequence to be producedaccording to a desired shape of this wander or wander sequence, as isfurther explained below in connection with FIGS. 3 and 4.

At the outputs 01 and 02 of the two individual dividers CNTa and CNTb isa phase comparator circuit COMg, the input side of which is connectedaccording to FIG. 1. At the output 03 of this phase comparator circuitCOMg, which is indicated as a circuit containing an AND gate, a low passfilter TPFg is connected whose output is connected to an output 04 ofthe circuit arrangement.

The respective desired wander or wander sequences can be taken at thetwo outputs 03 and 04 just mentioned. More detail will be provided onthis in connection with FIG. 4.

FIG. 2 shows a further development of the circuit arrangement shown inFIG. 1 as a second exemplary embodiment of the invention. According toFIG. 2, the counting arrangements includes two partial counters each, orCNT1 a and CNT1 b and CNT2 a and CNT2 b —for which the samespecifications apply that had been made with respect to the partialcounters CNTa, CNTb according to FIG. 1 —are each connected to theoutput of a separate oscillator circuit OSC1 and OSC2; the inputs of thetwo oscillator circuits OSC1 and OSC2 are each connected to the outputof a low pass filter TPF1 and TPF2.

Each of the two oscillator circuits OSC1 and OSC2 belongs to a separatePLL circuit, PLL1 and PLL2, within which they are each connected to theoutput of an associated phase comparator circuit COM1 and COM2 with itsrespective low pass filter TPF1 and TPF2. These phase comparatorcircuits COM1 and COM2 are connected in common through one of theirinputs to an input terminal identified by IN, to which, in this case,input signals are fed having relatively high frequency, for exampleimpulses with a frequency of 8 kHz, which can be derived from impulseswith a frequency of 16,384 MHz, for example. The generator circuitproducing these impulses must also operate here with very high precision(10⁻¹²) in order to be able to make available the desired wander orwander sequences. The 8 kHz input signal mentioned provides referenceimpulses or signals in the circuit arrangement according to FIG. 2. Theother inputs of both phase comparator circuits COM1 and COM2, each ofwhich is likewise represented as a circuit containing an AND gate, areconnected to an output of the counting arrangement that is connectedafter the respective oscillator circuit OSC1 and OSC2. In this case, theoutputs O1 and O2 of the partial counters CNT1 b and CNT2 b areconnected to the applicable inputs of the phase comparator circuit COM1and COM2. However, it is, in principle, also possible to connect theoutputs of the other partial counters CNT1 a and CNT2 a to theapplicable inputs of said phase comparator circuits COM1 and COM2.

As in the circuit arrangement shown in FIG. 1, control inputs of atleast the partial counter CNT2 b and, if necessary, also of partialcounter CNT2 a, are connected to control outputs of a control circuitCTR2 in the circuit arrangement shown in FIG. 2. These control outputscan correspond to the control circuit CTR1 shown in FIG. 1. Accordingly,the applicable control circuit CTR2 is connected to a control input atan input terminal Cin and to a signal input at output O2 of the partialcounter CNT2 b.

A phase comparator circuit COM3 is connected after the two countersshown in FIG. 2 to their outputs and includes on one hand the partialcounters CNT1 a and CNT1 b, and on the other the partial counters CNT2a, CNT2 b. At the output 03 of the phase comparator circuit, a low passfilter TPF3 is connected after it, whose output is connected to anoutput O4. The phase comparator circuit COM3 and the low pass filterTPF3 correspond to the phase comparator circuit COMg and the low passfilter TPFg in the circuit arrangement shown in FIG. 1.

FIGS. 3 and 4 explain the principle of generating wander or wandersequences as it is applied to this invention. In this regard, mentionshould be made that in principle both circuit arrangements according toFIGS. 1 and 2 operate in the same manner with regard to the generationof wander or wander sequences with very small frequencies below 10 Hz,and preferably below 1 Hz.

The diagram shown in FIG. 3 shows impulses or signals occurring atvarious circuit points of the circuit arrangements illustrated in FIG. 1and FIG. 2 along the time axis t. In the row identified by IN are theinput impulses occurring at the input terminals IN in the circuitarrangements according to FIGS. 1 and 2 that may occur with a relativelyhigh frequency of 8 kHz and which can be derived from a signal with afrequency of 16,384 MHz, for example. In the case of the circuitarrangement according to FIG. 1, these input impulses experience afrequency division in both partial counters CNTa and CNTb, so that finaloutput signals occur at the outputs O1 and O2 indicated in FIG. 1 thatare illustrated in the correspondingly named rows in FIG. 3, for examplewith a frequency of 8 kHz each. The same applies for the partialcounters CNT1 a, CNT1 b and CNT2 a, CNT2 b in the circuit arrangementaccording to FIG. 2.

According to FIG. 3, the leading edges of the impulses indicated in rowO2 are shifted with respect to the leading edges of the correspondingimpulses in row O1 by one cycle each of the impulses shown in the upperrow IN in FIG. 3 relative to the preceding time of observation shown,respectively. This shift occurs according to FIG. 3 relative to theimpulses shown in row O1 in one direction (to the right in FIG. 3). Inthe process, the change in this direction can occur over a time framecorresponding to n/2 of the period of the wander or wander sequence tobe issued, whereupon a change in the applicable leading edges of theimpulses shown in row O2 can then occur with respect to the leadingedges of the impulses shown in row O1 in the other direction (i.e.,according to FIG. 3 to the left) during a duration of n within theperiod of the wander or wander sequence to be issued. Then, a change canagain finally take place in the leading edges of the impulses shown inrow O2 relative to the leading edges of the corresponding impulses shownin row O1 in FIG. 3 in the manner explained above (i.e., to the right inFIG. 3) during a duration of n/2 within the period of the wander orwander sequence to be issued.

The shift explained above in the leading edges of the impulses of theoutput signal shown in row O2 in FIG. 3 with respect to the leadingedges of the impulses of the output signal shown in row O1 in FIG. 3occurs by correspondingly adjusting the partial counter C22 shown inFIG. 1 or of the partial counter CNT2 a shown in FIG. 2 by means of thecontrol circuit CTR1 or CTR2 connected to its control inputs. In theprocess, this control circuit CTR1 or CTR2 changes, firstly, the countcycle of the applicable partial counter C22 or CNT2 a with respect tothe count cycle of the other corresponding partial counter C12 or CNT1 awithin the period of the wander or of the wander sequence to beproduced, and secondly, this change occurs according to the desiredshape of this wander or wander sequence. In order to further clarifythis statement, reference is made to the diagram shown in FIG. 4.

The diagram according to FIG. 4 shows in an amplitude-time axis diagramthe temporal shape of the output signals occurring at the output O3 andat output O4 in the circuit arrangement according to FIG. 1 and FIG. 2(wander or wander sequence) along the time axis t. In the process, theoutput signal occurring at the output, i.e., output terminal O3 shows atriangular shaped curve having a positive value within the time framefrom 0 to n and a negative shape within the time frame from n to 2ndirectly adjacent to it. The time frame from 0 to 2n represents oneperiod of the wander or wander sequence to be produced.

The triangular shaped output signal with the stepped stages is producedbased on the relationships that had been explained before in connectionwith FIG. 3, with respect to the impulses or output signals shown inrows O1 and O2. In the process, the respective step height (amplitude)of this output signal shown in FIG. 4 by O3 depends on the phasedifference between the output signals occurring in rows O1 and O2according to FIG. 3, and accordingly at the corresponding circuit pointsaccording to FIG. 1 and FIG. 2, the output signals being processed bythe phase comparator circuit COMg or COM3. However, the respective stepwidth (in the direction of the time axis) depends on the duration duringwhich the amplitude mentioned before is to be issued within the period(0-2n) of the wander or wander sequence to be produced. This means thata corresponding adjustment of the partial counter C22 occurs by means ofthe control circuit CTR1 or CTR2 for this duration.

In order to be able to execute the adjustment of the partial counter C22mentioned, a corresponding control signal can be fed to the controlcircuit CTR1 at its control input or input terminal Cin, which firstestablishes the respective duration during which the respectiveadjustment of the partial counter C22 or CNT2 a is to remain (stepwidth), and which secondly establishes the number of changes of thepartial counter C22 or CNT2 a for the change of its counter positionrelative to the counter position of the other corresponding partialcounter C12 or CNT1 a (amplitude), as had been explained in connectionwith FIG. 3. To be able to execute this control action, the controlcircuits CTR1 and CTR2 are each connected to a signal input at thecircuit point or output O2 according to FIGS. 1 and 2.

The sinusoidal output signal O4 is then formed from the output signal O3shown in FIG. 4 by means of the low pass filter TPFg or TPF3 in thecircuit arrangement according to FIG. 1 or according to FIG. 2, which isissued by the corresponding output or output terminal O4 of the circuitarrangement according to FIGS. 1 and 2. This means that a smoothing ofthe triangular output signal O3 leads to output signal O4. Acorresponding smoothing of the output signal of the phase comparatorcircuit COM2 takes place as well in the circuit arrangement shown inFIG. 2 by means of the low pass filter TPF2. This smoothing results in astable control voltage being fed to the oscillator circuit OSC 2according to FIG. 2, which leads to the issuance of an oscillator outputsignal with stable frequency.

Based on the count values given above for the impulses occurring at therespective input terminal IN as well as at the outputs O1 and O2 in thecircuit arrangements according to FIGS. 1 and 2, a wander or wandersequence can be obtained from the output O3 or O4 of this circuitarrangement, as shown in FIG. 4 with a frequency of 12 μHz, for example,which corresponds to a period T=23,148 h. In the process, the shapeshown in FIG. 4 of the wander sequence can occur [be produced] in 295steps for example (time axis t).

Finally, mention is made that the phase comparator circuits contained inthe circuit arrangements shown in FIGS. 1 and 2 are preferablyphase-sensitive phase comparator circuits, i.e., phase detectors or Type2 PD systems as they are called in the literature (see for example thebook “Einfóhrung in die PLL-Technik,”[Introduction to PLL Technology],H. Geschwinde, Verlag Priedr. Vieweg & Sohn, Braunschweig/Wiesbaden,1980, beginning at page 118, and the book “Theorie und Anwendung desphase-locked-loops” [Theory and Application of Phase Locked Loops],Roland Best, AT Verlag Aarau/Schweiz, 1993, pages 96-99).

Otherwise, the circuit arrangement according to the invention is notjust suited for the generation of sinusoidal wander or wander sequences,as had been described above, but that in general also wander or wandersequences with other forms can be generated. As can be seen, theestablishment of these forms occurs through correspondingly issuingcontrol signals from the control circuit CTR1 or CTR2 in the circuitarrangements according to FIGS. 1 and 2, which are separately controlledfrom them. Referring to the circuit arrangement according to FIG. 2, itshould also be mentioned that its oscillator circuits OSC1 and OSC2 canbe separately adjusted if necessary in order to generate an even largervariety of wander or wander sequences than is possible using the controlcircuit CTR2.

1. A circuit to produce wander or wander sequences having frequenciesbelow 10 Hz comprising; a frequency divider circuit that receivesimpulse signals of relatively high frequency as incoming inputs andissues impulse signals of divided frequency as its output, from whichthe respective wander or wander sequence is formed, the frequencydivision circuit having two dividers, each of which encompasses acounting arrangement, both of which receive as incoming inputs theimpulse signals mentioned having the relatively high frequency, thecount cycle of one counting arrangement is changed with respect to thecount cycle of the other counting arrangement within the period of therespective wander or wander sequence to be produced according to adesired shape of the wander or wander sequence; and a phase comparatorcircuit is connected to outputs of both counting arrangements, from theoutput of which the respective wander or the respective wander sequencecan be taken.
 2. The circuit arrangement according to claim 1, wherein alow pass filter is connected after the phase comparator circuit.
 3. Thecircuit arrangement according to claim 1, wherein each countingarrangement is connected to the output of its own oscillator circuit. 4.The circuit arrangement according to claim 3, wherein each oscillatorcircuit belongs to a separate PLL circuit.
 5. The circuit arrangementaccording to claim 2, wherein each counting arrangement is connected tothe output of its own oscillator circuit.